FPGALibertron2019-03-08T11:56:14+09:00

FPGA

45nm

28nm

20nm

16nm

45nm

Value	Features
Programmable System Integration	High pin-count to logic ratio for I/O connectivity Over 40 I/O standards for simplified system design PCI Express® with integrated endpoint block
Increased System Performance	Up to 8 low power 3.2Gb/s serial transceivers 800Mb/s DDR3 with integrated memory controller
BOM Cost Reduction	Cost-optimized for system I/O expansion MicroBlaze™ processor soft IP to eliminate external processor or MCU components
Total Power Reduction	1.2V core voltage or 1.0V core voltage option Zero power with hibernate power-down mode
Accelerated Design Productivity	Enabled by ISE® Design Suite—a no-cost, front-to-back FPGA design solution for Linux and Windows Fast design closure using integrated wizards

28nm

Value	Features
Programmable System Integration	Up to 2M logic cells, VCXO component, AXI IP, and AMS integration
Increased System Performance	Up to 2.8 Tb/s total serial bandwidth with up to 96 x 13.1G GTs, up to 16 x 28.05G GTs, 5,335 GMACs, 68Mb BRAM, DDR3-1866
BOM Cost Reduction	Up to 40% lower cost than multi-chip solution
Total Power Reduction	Up to 70% lower power than multi-chip solution
Accelerated Design Productivity	Scalable optimized architecture, comprehensive tools, IP and TDPs

Value	Features
Programmable System Integration	Up to 478K logic cells, VCXO component, AXI IP, and AMS integration
Increased System Performance	Up to 32 x 12.5G GTs, 2,845 GMACs, 34Mb BRAM, DDR3-1866
BOM Cost Reduction	Half the price of similar density 40nm devices
Total Power Reduction	50% lower power than previous generation 40nm devices
Accelerated Design Productivity	Scalable optimized architecture, comprehensive tools, IP and Boards and Kits

Value	Features
Programmable System Integration	Up to 215K LCs; AXI IP and Analog Mixed Signal integration
Increased System Performance	Up to 16 x 6.6G GTs, 930 GMAC/s, 13Mb BRAM, 1.2Gb/s LVDS, DDR3-1066
BOM Cost Reduction	Small wire bond packaging and up to $5 analog component savings
Total Power Reduction	65% lower static and 50% lower power than 45nm generation devices
Accelerated Design Productivity	Scalable optimized architecture, comprehensive tools and IP

Value	Features
Programmable System Integration	High pin-count to logic ratio for I/O connectivity MicroBlaze™ processor soft IP Integrated security and monitoring
Increased System Performance	30% faster performance than 45nm generation devices Up to 1.25Gb/s LVDS 25.6Gb/s peak DDR3-800 memory bandwidth with flexible, soft memory controller
BOM Cost Reduction	XADC and SYSMON for integrating discrete analog and monitoring circuitry Cost-optimized for system I/O expansion
Total Power Reduction	1.0V core voltage or 0.95V core voltage option 50% lower total power than 45nm generation devices
Accelerated Design Productivity	Enabled by Vivado® HLx Design Suite WebPack™ Correct-by-construction block-level design with Vivado IP Integrator Scalable optimized architecture, comprehensive tools and IP reuse

20nm

Value	Deliverables
Programmable System Integration	Up to 5.5M System Logic Cells at 20nm using 2^nd generation 3D IC Integrated 100G Ethernet MAC and 150G Interlaken cores
Increased System Performance	Up to two speed-grade improvement with high utilization 30G transceivers for chip-to-chip, chip-to-optics, 28G backplanes 16G backplane capable transceivers at half the power 2400Mb/s DDR4 for robust operation over varying PVT
BOM Cost Reduction	Up to 50% lower cost – half the cost per port for Nx100G systems VCXO and fractional PLL integration reduces clocking component cost 2400Mb/s DDR4 in a mid-speed grade
Total Power Reduction	Up to 40% lower power vs. previous generation Fine granular clock gating with ASIC-like clocking Enhanced System Logic Cell packing reduces dynamic power
Accelerated Design Productivity	Footprint compatibility with Kintex® UltraScale devices for scalability Seamless footprint migration from 20nm planar to 16nm FinFET Co-optimized with Vivado® Design Suite for rapid design closure

Value	Deliverables
Programmable System Integration	Up to 1.5M System Logic Cells leveraging 2^nd generation 3D IC Multiple integrated PCI Express® Gen3 cores
Increased System Performance	8.2 TeraMACs of DSP compute performance Up to two speed-grade improvement with high utilization 16G backplane-capable transceivers, up to 64 per device 2,400Mb/s DDR4 for robust operation over varying PVT
BOM Cost Reduction	System integration reduces application BOM cost by up to 60% 12.5Gb/s transceivers in slowest speed grade 2,400Mb/s DDR4 in a mid-speed grade VCXO integration reduces clocking component cost
Total Power Reduction	Up to 40% lower power vs. previous generation Fine granular clock gating with UltraScale devices ASIC-like clocking Enhanced system logic cell packing reduces dynamic power
Accelerated Design Productivity	Footprint compatibility with Virtex® UltraScale devices for scalability Co-optimized with Vivado® Design Suite for rapid design closure

16nm

Value	Features
Programmable System Integration	Up to 8GB of HBM Gen2 integrated in-package Up to 500Mb of on-chip memory integration Integrated 100G Ethernet MAC with KR4-FEC and 150G Interlaken cores Integrated blocks for PCI Express Gen 3×16
Increased System Performance	Over 2X system-level performance per watt over Virtex-7 FPGAs Up to four speed-grade improvement with high utilization Up to 128-33G transceivers deliver 8.4 Tb of serial bandwidth 58G PAM4 transceivers with KP4-FEC enable data transmission at 50G+ line rates 460GB/s HBM bandwidth, and 2,666 Mb/s DDR4 in a mid-speed grade
BOM Cost Reduction	A 5:1 card reduction for 1 Tb MuxSAR transponder UltraRAM for on-chip memory integration VCXO and fractional PLL integration reduces clocking component cost
Total Power Reduction	Up to 60% lower power vs. 7 series FPGAs Voltage scaling options for performance and power Tighter logic cell packing reduces dynamic power
Accelerated Design Productivity	Seamless footprint migration from 20nm planar to 16 nm FinFET+ Co-optimized with Vivado Design Suite for rapid design closure SmartConnect technology for intelligent IP integration

Value	Deliverables
Programmable System Integration	Up to 1.2M System Logic Cells UltraRAM for on-chip memory integration Integrated 100G Ethernet MAC with RS-FEC and 150G Interlaken cores
Increased System Performance	6.3 TeraMACs of DSP compute performance Over 2X system-level performance per watt over Kintex-7 FPGAs 16G and 28G backplane-capable transceivers 2,666 Mb/s DDR4 in the mid-speed grade
BOM Cost Reduction	12.5 Gb/s transceivers in slowest speed grade VCXO and fractional PLL integration reduces clocking component cost
Total Power Reduction	Up to 60% lower power vs. 7 series FPGAs Voltage scaling options for performance and power Tighter logic cell packing reduces dynamic power
Accelerated Design Productivity	Co-optimized with Vivado Design Suite for rapid design closure SmartConnect technology for intelligent IP integration

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